The present invention relates to a memory refreshing system for refreshing a dynamic memory (DRAM), and in particular to a memory refreshing system that executes not only a normal refresh operation between memory access operation by a CPU (central processing unit), but also a self-refresh operation for self-sufficiently refreshing memory banks. More specifically, the present invention pertains to a memory refreshing system that, to reduce the power consumption, dynamically switches between normal refresh and self-refresh operations for memory bank units.
In accordance with recent technical developments, various types of personal computers (PCs), such as desktop computers for use in offices and battery-operated notebook computers for use in mobile environments, have been generated and are available on the market.
A basic configuration for these computer systems includes a CPU, which functions as a central controller, and a main memory, to which the CPU accesses. The CPU executes programs loaded on the main memory, and sequentially writes the results obtained by program execution into work areas in banks of the main memory so that the computer processing is performed.
For the main memory, DRAM (dynamic RAM) is generally used because DRAM has a simple cell structure and increasing the capacity of memory composed of DRAM is easier than increasing the capacity of memory composed of SRAM (static RAM), and also because the cost per DRAM memory capacity is generally less than that of SRAM. The DRAM memory cells in the memory are arranged as a matrix. In order to address memory cells individually, first, row addresses and row address strobe (RAS) signals are supplied, and then, column addresses and column address strobe (CAS) signals are supplied.
In the DRAM memory cells, data are capacitively accumulated and stored as individual electric charges. Thus, when data are written to the memory cells and are left for an extended period of time, the charges leak and the stored data are lost. To prevent such data loss, the written data should be refreshed (i.e., re-written) at a predetermined time intervals. A basic refresh operation consists of the accessing to a specific memory cell row to refresh all of the cells along that row. In order to refresh all of the row addresses, a refresh address counter is required that designates refresh addresses sequentially, and means for providing a refresh cycle, or for issuing a refresh request at a predetermined period of time. It should be noted that, in general, a refresh address counter is so designed that it automatically increments a count value upon each refresh cycle.
The following explanation is with regard to RAS-only refresh and CAS-before-RAS refresh. The refresh control methods are, for example, an xe2x80x9cRAS-only refreshxe2x80x9d method and a xe2x80x9cCAS-before-RAS refreshxe2x80x9d method. The RAS-only refresh method is one where a refresh operation is controlled by using only row address strobe (RAS) signals. For this method, a refresh address counter that designates refresh row addresses must be provided outside the memory.
The CAS-before-RAS refresh method is one where a refresh request is supplied to the memory by activating a row address strobe (RAS) signal immediately after the transmission of a column address strobe (CAS) signal, i.e., by using the form CAS-before-RAS. Since an RAS signal is always activated first during a common memory access operation, CAS-before-RAS refreshing is possible. According to this method, so long as a refresh address counter is provided inside the memory, refreshing is performed substantially the same as it is by the RAS-only refresh method. In addition, an external address counter is not necessary. Recent DRAM products that have a memory capacity of 256K bits or larger generally include the CAS-before-RAS function.
The following explanation is with regard to normal refreshing and self-refreshing. From the view point of operabonal methods, a refresh control operation can be classified as either a xe2x80x9cnormal refreshxe2x80x9d or xe2x80x9cself-refreshxe2x80x9d operation. A normal refresh operation, as is indicated by the words, is an operation performed while a computer system is in a normal operation mode, i.e, between memory accesses by the CPU. Since a normal refresh circuit is so designed that it employs a high processing speed, in accordance with the access operation by the CPU, it tends to require a large amount of power consumption. A normal refresh operation is usually performed once every 15 xcexcsec, with a refresh cycle of 200 to 500 nsec and a power consumption of 100 mA, and the average current used per hour unit is 2 to 5 mA. As this is the power consumed per DRAM chip, and since four to eight DRAM chips are generally mounted in a PC, the total current consumed during a normal refresh operation can be as much as several tens of mA.
On the other hand, self-refreshing has been developed to reduce the current required for refresh operation, and for this operation, the refreshing is performed internally, by a memory device itself. In order to conduct self-refreshing, thememory device requires means for acquiring a refresh cycle at predetermined intervals, and a refresh address counter to designate a refresh address for each refresh cycle.
Since self-refreshing is performed during when the CPU is not accessing to the memory, self-refreshing may be asynchronized with the operation rate of the CPU. The self-refreshing operation requires the use of only a minimum current (200 to 300 xcexcA) at a longer cycle period so that the data loss in each memory cell can be prevented, self-refreshing can save the power consumption. In addition, as self-refreshing can be performed only inside the memory device, devices other than the memory can be powered down so that the power management effect can be expected. Another aspect bearing on the effectiveness of self-refreshing is that, when viewed from outside the memory, DRAM can be employed as SRAM (as pseudo SRAM) that does not need the refresh operation.
Most computer systems, in which memory backups is taken into consideration, have both the normal refresh function and the self-refresh function. FIG. 6 is a schematic diagram illustrating the arrangement of a computer system that has both the normal refresh function and the self-refresh function. A memory device, and a CPU and an I/O device that provides access to it are connected to each other by a bus. Outside the memory device are provided a normal refresh circuit that performs a relatively fast refresh operation while the CPU is accessing to the memory, and a clock that supplies a relatively short interval signal to the normal refresh circuit. Inside the memory device are provided a self-refresh circuit that performs a relatively slow refresh operation, and an internal clock that supplies a relatively long interval signal to the self-refresh circuit. In addition, a switch is provided to select either the normal refresh circuit or the self-refresh circuit for refreshing the memory device.
The recent memory systems have a plurality of memory banks, for each of which a set of RAS and CAS signals is assigned, and most of the memory system can perform a self-refresh operation for each memory bank. The normal refresh circuit need only transmit a control signal to a memory bank using the CAS-before-RAS method to provide a refresh cycle for the memory bank. Inside the memory bank, an incorporated refresh address counter automatically increments an address upon each refresh cycle. Further, the memory system enters self-refresh mode and activates the incorporated self-refresh function in response to that both the RAS and CAS input to the memory bank are kept in the active state for a predetermined period of time.
The following explanation is with regard to reduction in power consumed for memory refreshing. For battery-operated notebook computers, a reduction in the power consumed is an urgent matter, and is required to extend the battery duration in mobile environments. The power required by such a computer system for memory refreshing can also not be ignored. And as was hereinbefore described, since self-refreshing requires less power than normal refreshing, the use of self-refreshing is desirable whenever possible.
However, as self-refreshing is performed at slow speed asynchronously with the CPU operation, as hereinbefore presented, memory bank access (including both read and write access) is disabled in the self-refresh mode. For the stability of the operation, a common DRAM chip is so constructed that once the entry to the self-refresh mode has been triggered, recovery of the memory bank to the normal refresh mode can not be started unless the memory bank has completely entered to the self-refresh mode. Therefore, a delay time of about 100 xcexcsec is required for the recovery by the memory bank from the self-refresh mode to the normal refresh mode. When the memory bank is accessed during the recovery period, the transferred data may be damaged or lost, and accordingly, the security of the system operation could be impaired.
Conventionally, therefore, the security of the system operation is regarded as more important than the power management. While a CPU is executing a normal operation, self-refreshing is not conducted and only normal refreshing is performed. More specifically, self-refreshing is employed only during a period wherein the computer system has entered a low power mode, such as a suspended mode, and has completely halted its normal operation. Even when the CPU is accessing only a specific memory bank, the other memory banks that are not being accessed are not switched to the self-refresh mode.
It is therefore one objective of the present invention to further reduce the average current required for an entire computer system by an improved method of reducing the current required for memory refreshing.
It is another objective of the present invention to provide an improved memory refreshing system including, as a feature, not only a normal refresh function for performing refreshing in a normal operational mode, but also a self-refresh function for internally performing memory bank refreshing.
It is an additional objective of the present invention to provide an improved memory refreshing system that can further save the power consumption by dynamically executing in an improved manner a self-refresh operation, even though the computer system is in a normal operational mode.
To achieve the above objectives and others made obvious by this disclosure, according to a first aspect of the present invention, a memory refreshing system, for a memory system including a plurality of memory banks, comprises: (a) normal refreshing means for executing a memory refresh operation for the memory system; (b) memory access monitoring means, provided for each of the memory banks, for detecting a request to access to a corresponding memory bank; and (c) self-freshing means, provided for each of the memory banks, for, when a predetermined period of time has elapsed since a last access to the corresponding memory bank, suspending the memory refresh operation by the normal refreshing means for the memory bank and performing a self memory refresh operation within the memory bank.
According to a second aspect of the present invention, a memory refreshing system, for a memory system including a plurality of memory banks, comprises: (a) memory refreshing means, provided in each of the memory banks, for performing a refresh operation within a corresponding memory bank by units of rows in response to a refresh request; (b) first memory refresh control means for supplying a refresh request to the memory system every first time period (P1); (c) second memory refresh control means, provided for each of the memory banks, for supplying a refresh request to the corresponding memory bank every second time period (P2) that is longer than the first time period (P1); (d) memory access monitoring means, provided for each of the memory banks, for detecting an access to the corresponding memory bank; (e) a timer, provided for each of the memory banks, for generating a timer output when a first predetermined time (T1) has elapsed since a last access to the corresponding memory bank, and cancelling a counted timer value in response to the next access to the corresponding memory bank; and (f) a selector, provided for each of the memory banks, for selecting one of the refresh requests from the first and the second memory refresh control means in accordance with the timer output.
According to a third aspect of the present invention, a memory refreshing system, for a memory system including a plurality of memory banks, comprises: (a) memory refreshing means, provided for each of the memory banks, for performing a refresh operation within a corresponding memory bank by units of rows in response to a refresh request; (b) first memory refresh control means for supplying a refresh request to the memory system every first time period (P1); (c) second memory refresh control means, provided for each of the memory banks, for supplying a refresh request to the corresponding memory bank every second time period (P2) that is longer than the first time period (P1); (d) memory access monitoring means, provided for each of the memory banks, for detecting an access to the corresponding memory bank; (e) a timer, provided for each of the memory banks, for generating a timer output when a first predetermined time (T1) has elapsed since a last access to the corresponding memory bank, and cancelling a counted timer value in response to the next access to the corresponding memory. bank; (f) a selector, provided for each of the memory banks, for selecting one of the refresh requests from the first and the second memory refresh control means in accordance with the timer output; and (g) a wait request means, provided for each of the memory banks, for, when an access to the corresponding memory bank is. detected while the timer output is active, requesting that an access requester to delay a memory access.
The refresh operation of the first memory refresh control means corresponds to a so-called xe2x80x9cnormal refreshxe2x80x9d operation, and a refresh operation of the second memory refresh means corresponds to a xe2x80x9cself-refreshxe2x80x9d operation.
In the memory refreshing system as recited in the second and the third aspects, the first memory refresh control means may include means for supplying a refresh request by activating a row address strobe (RAS) signal immediately after transmission of a column address strobe (CAS) signal. This is because CAS-before-RAS memory refreshing has been adopted for many recent memory systems.
In the memory refreshing system as recited in the second and the third aspects, the second memory refresh control means may begin to supply the refresh request in response to that both a received column address strobe (CAS) signal and a received row address strobe (RAS) signal are kept in the active state for a second predetermined time (T2) or longer. This is because many recent self-refreshing functions are so designed as to wake when there is no memory access for a predetermined time period, i.e., when RAS and CAS signals are kept active for a predetermined period of time or longer.
In the memory refreshing system as recited in the second and the third aspect, the memory access monitoring means may include: means for receiving a column address strobe (CAS) signal and a row address strobe (RAS) signal that are transmitted to the corresponding memory bank; means for detecting an access to the corresponding memory bank when the column address strobe (CAS) signal is activated immediately after the row address strobe (RAS) signal; and means that does not detect an access to the corresponding memory bank when the row address strobe (RAS) signal is activated immediately after the column address strobe (CAS) signal. The RAS-before-CAS method is employed for normal memory access, while the CAS-before-RAS method is employed for a refresh request. Taking the switching of a refresh mode into consideration, the normal refresh operation does not need to be regarded in the same manner as is the normal memory access. The memory access monitoring means ignores the CAS-before-RAS request, and as a result, so that the timer counts the time that has elapsed since a last memory access, while excluding the time for the CAS-before-RAS request.
In the memory refreshing system as recited in the second and the third aspects, the selector may include: means for accepting the refresh request from the first memory refresh control means during a period the timer output is inactive; and means for rejecting the refresh request from the first memory refresh control means when the timer output is activated.
In the memory refreshing system as cited in the second and the third aspects, the means for rejecting the refresh request from the first memory refresh control means may include means for activating both the row address strobe (RAS) signal and the column address strobe (CAS) signal to be transmitted to the second memory refresh control means. With this arrangement, the refresh requests from the first and the second memory refresh control means are selectively employed.
Most of the recent memory systems have a plurality of memory banks, for each of which is assigned a set composed of a RAS signal and a CAS signal. Therefore, the memory system can manage a memory access of each memory bank. In the memory refreshing system cited in the above aspects of the present invention, memory accesses by a CPU are monitored for each memory bank. A normal refresh operation is performed continuously for a memory bank that is frequently accessed. On the other hand, for a memory bank that is not accessed during the first predetermined time (T1) or longer, the operation is dynamically switched to a self-refresh mode.
A normal refresh operation is performed in a period between memory access operation by the CPU. A memory refresh request is generally handled prior to a memory access request. Since this access operation is executed in accordance with the operating speed of the CPU, it accordingly requires a large current. On the other hand, a self-refresh operation is performed asynchronously with the operation of the CPU using a minimum current and the slowest cycle at which stored data are not lost, so that self-refreshing is effective in saving the power consumption. According to the present invention, not only in the low-active condition, such as a suspend condition, but also during the normal operation of the computer system, the refresh operation can be dynamically shifted to the self-refresh mode in accordance with the frequency of access to each memory bank. Taking into account the xe2x80x9cprinciple of localityxe2x80x9d, that teaches a currently executing program frequently accesses only a specific memory area, relatively many memory banks can be switched to the self-refresh mode during normal operation, and the power management performed in accordance with the present invention is highly effective.
In addition, since self-refreshing is asynchronously performed relative to the operation of the CPU, the operational mode must be recovered to the normal refresh mode when the memory access process to a memory bank is resumed, and a certain delay time, as hereinbefore presented in an examplary manner as 100 xcexcsec is required for the recovery to be effected. According to the memory refreshing system in the third aspect, when access of a memory bank in a self-refresh mode is requested, a wait request is issued to the access requester, that is, a memory controller, to delay the start of memory access. Thus, time for recovering to the normal refresh mode is afforded for the memory bank in the self-refresh mode. Although this time constitutes memory access overhead, since once the memory bank is returned to the normal operation mode the accessing of that memory bank will continue for a period of time according to the principle of locality, and another memory bank enters the self-refresh mode by turns. When viewed as a part of the total system operation time, the overhead represented by the recovery time is negligible and can be ignored.
Therefore, according to the memory refreshing system of the present invention, self-refreshing is dynamically performed even during the normal mode, and as a result, a reduction in the power consumption can be realized.
Other objects, features, and advantages of the present invention will become apparent in due course during the detailed description of the embodiment of the present invention, which will be given while referring to the accompanying drawings.